The present disclosure relates to supplying power in a mixed signal integrated circuit (IC), and in particular to linear regulator for mixed signal ICs.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
An integrated circuit (IC) that has both analog circuits and digital circuits on a single semiconductor die is commonly referred to as a mixed signal IC. In a mixed signal IC, the digital circuitry typically operates at a high frequency and the analog circuitry operates at DC or a relatively lower frequency as compared to the digital load. The fast-changing digital signals can send noise to the analog circuitry. One path for this noise can occur in the power supply section of the IC. The power supply section should exhibit immunity to noise transients that may arise when the analog and digital circuitry are driven. A common approach is to provide separate drive voltages for the analog circuitry and for the digital circuitry. The power supply section typically provides a current source that is proportional to bandgap voltage. Since the current source may be used for biasing or to produce a reference, the current source should also be as noise-free as possible.
FIG. 1 shows a typical configuration for a power supply section in a mixed signal IC. A first operational transconductance amplifier (OTA) 12 is configured with two source followers N1, N2. An output current of the OTA 12 sets up a voltage VG—BIAS across output capacitor C1 that serves to bias transistors N1, N2. Accordingly respective drive voltages V2.5—ANA, V2.5—DIG serve as separate drive voltages for respective analog and digital circuitry, represented in the figure as “loads”. The resistor network R1 and R2 are typically configured to produce drive voltages V2.5—ANA, V2.5—DIG on the order of 2.5 V.
During operation, the loading conditions in the analog circuitry or the digital circuitry may affect the drive voltages. For example, loading in the analog circuitry may suddenly increase, causing a sudden drop in the voltage level across the capacitor CL1 and bringing V2.5—ANA below an acceptable value. A similar occurrence may arise for the digital circuitry. If the level for V2.5—DIG falls below a threshold value, the digital circuitry may go into a sleep state or turn off completely. A possible solution is to place a large capacitor Cx to buffer variations in VG—BIAS. However, such a capacitor may have a prohibitively large capacitance.
Digital circuitry present an additional concern. Logic gates in the digital circuitry may generate considerable switching noise during operation. These noise transients may be coupled back to the gate of transistor N2 through an action known as “charge coupling.” Since the transistor N2 operates as a voltage driver, the device must have relatively large physical dimensions in order to source sufficient current to operate properly. However, the overlap of the gate electrode with the source/drain electrodes in a large dimension device may result in significant capacitive coupling between the gate and the source (CGS). Accordingly, any noise transients in the digital logic sensed by the source terminal of transistor N2 may be coupled back to the gate terminal of the transistor and thus influence the VG—BIAS voltage level that is connected to the gate. Variations in the VG—BIAS voltage would result in fluctuations in the drive voltage V2.5—ANA, which could adversely affect operation of the analog circuitry.
FIG. 1 also includes a second OTA 14 that is configured with transistors P1 and P2 connected in a current mirror configuration. Output current I of the OTA 14 is proportional to the bandgap voltage VBG and 1/(R3+R4). The output current I drives the current mirror P1/P2, which is powered by a power supply voltage VDD, to produce a mirrored current IVBG. The current mirror P1/P2 therefore serves as a current source that is proportional to the bandgap voltage. Separating the circuit that serves as the current source (namely, current mirror P1/P2) from the circuit that generates the drive voltages allows for producing a current that exhibits low noise characteristics, although at the cost of space-consuming circuitry. A lower cost alternative is to configure the current mirror P1/P2 with the OTA 12, thus obviating the OTA 14. However, the resulting current source may be more susceptible to noise due to switching transients in the digital circuit.